GraphicsV API

Document dated Monday the 9th of January, 2006

GraphicsV

GraphicsV is vector number 42 (&2A)

R4 = reason code .. Bits 31..24 = display number, default 0


VSync interrupt occured (Driver -> Kernel)
  R4 = 1
out: R0-R3 corrupt

Set mode
  R4 = 2
  R0 -> VIDC list type 3

Set interlace
  R4 = 3
  R0 = 0 or 1 (off or on)

Set blank
  R4 = 4
  R0 = 0 or 1 (unblank or blank)
  R1 = DPMS state (0 -3)

Update pointer
  R4 = 5
  R0 = flags (bit 0 => enable, bit 1 => shape changed)
  R1 = x pos
  R2 = y pos
  R3 -> shape descriptor

 R3 points to shape_t descriptor block:
   typedef struct shape_t
   {
	uint8	width;	    /* unpadded width in bytes (see notes) */
	uint8	height;	    /* in pixels */
	uint8	padding[2]; /* 2 bytes of padding for field alignment */
	void   *buffLA;	    /* logical address of buffer holding pixel data */
	void   *buffPA;	    /* corresponding physical address of buffer */
   }

 Notes:
 1) if flags bit 0 is 0 (pointer off), x, y, shape are undefined
 2) the shape data from RISC OS is always padded with transparent pixels
    on the rhs, to a width of 32 pixels (8 bytes)
 3) pointer clipping is the responsibility of the HAL (eg. may be able to
    allow display of pointer in border region on some h/w)
 4) buffer for pixel data is aligned to a multiple of 256 bytes or better

 This call is made by the OS at a time to allow smoothly displayed changes
 (on a VSync)

Set DAG
  R4 = 6
  R0 = DAG (0 = display init, 1 = base, 2 = limit, 3 = vdu init)
  R1 = physical address

Vet mode (reserved)
  R4 = 7
  R0 = VIDC list
  R1 = workspace ?
out: R0 = 0 if OK
  
Features
  R4 = 8
out:
  R0 = flags word (bit 0 => hardware scroll)
		  (bit 1 => hardware pointer)
		  (bit 2 => interlace with progressive framestore)
		  (bit 3 => separate framestore)
		  (bit 4 => no VSyncs generated)
  R1 = pixel formats (bits 0-5 => 2^n bpp supported)
  R2 = buffer alignment requirement in bytes (power of 2)

Framestore information
  R4 = 9
out:
  R0 = framestore physical base address
  R1 = framestore size
  R4 = 0 if external framestore used, preserved if not

Write palette entry
  R4 = 10
  R0 = type (0 = normal entry, 1 = border, 2 = pointer)
  R1 = palette entry (&BBGGRRSS)
  R2 = palette index

Write palette entries
  R4 = 11
  R0 = type (0 = normal entry, 1 = border, 2 = pointer)
  R1 -> palette entry table
  R2 = first palette index
  R3 = number of entries

Read palette entry
  R4 = 12
  R0 = type (0 = normal entry, 1 = border, 2 = pointer)
  R1 = palette entry (&BBGGRRSS)
  R2 = palette index
Out:
  R1 = palette updated

Render
  R4 = 13
  R0 = flags
	 bit 0 = synchronise
	 bit 1 = synchronise if unclaimed
  R1 = operation
  R2 -> parameter block

IIC_Op
   R4 = 14
   R0 = card<<28 + channel<<24 + I2Ccmnd << 16 + address
                                 I2Ccmnd = 1 for read, 0 write
   R1 ->dma address
   R2 = byte count
 Out:
   R0 = 0 or error block
   R1 updated
   R2 updated   

Select Head
  R4 = 15
  R0 = head to select (in multihead graphics card)

Render calls:

  R1 = 0   NOP
  no parameters (R2  undefined) - NOP
   
  R1 = 1   Copy rectangle
  R2+0 = source left
  R2+4 = source bottom
  R2+8 = dest left
  R2+12 = dest bottom
  R2+16 = width-1
  R2+20 = height-1
  
  
  R1 = 2   Fill rectangle
  R2+0 = left
  R2+4 = top
  R2+8 = right
  R2+12 = bottom
  R2+16 -> OraEor block (on a 64-byte boundary)